Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 365
1: NAND Flash in READY State
8
R
/
NDFC_RB_STATE0
NAND Flash R/B 0 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State
7:5
/
/
/
4
R
0
NDFC_STA
0: NDFC FSM in IDLE state
1: NDFC FSM in BUSY state
When NDFC_STA is 0, NDFC can accept new command and process
command.
3
R
0
NDFC_CMD_FIFO_STATUS
0: Command FIFO not full and can receive new command
1: Full and waiting NDFC to process commands in FIFO
Since there is only one 32-bit FIFO for command. When NDFC latches one
command, command FIFO is free and can accept another new command.
2
R/W
0
NDFC_DMA_INT_FLAG
When it is 1, it means that a pending DMA is completed. It will be clear after
writing 1 to this bit or it will be automatically clear before FSM processing an
new command.
1
R/W
0
NDFC_CMD_INT_FLAG
When it is 1, it means that NDFC has finished one Normal Command Mode
or one Batch Command Work Mode. It will be clear after writing 1 to this bit
or it will be automatically clear before FSM processing an new command.
0
R/W
0
NDFC_RB_B2R
When it is 1, it means that NDFC_R/B# signal is transferred from BUSY state
to READY state. It will be clear after writing 1 to this bit.
5.2.6.3. NDFC Interrupt and DMA Enable Register(Default Value: 0x00000000)
Offset: 0x08
Register Name: NDFC_INT
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2
R/W
0
NDFC_DMA_INT_ENABLE
Enable or disable interrupt when a pending DMA is completed.
1
R/W
0
NDFC_CMD_INT_ENABLE
Enable or disable interrupt when NDFC has finished the procession of a
single command in Normal Command Work Mode or one Batch Command
Work Mode.
0: Disable
1: Enable
0
R/W
0
NDFC_B2R_INT_ENABLE
Enable or disable interrupt when NDFC_RB# signal is transferring from BUSY
state to READY state
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