Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 366
0: Disable
1: Enable
5.2.6.4. NDFC Timing Control Register(Default Value: 0x00000000)
Offset: 0x0C
Register Name: NDFC_TIMING_CTL
Bit
R/W
Default/Hex
Description
31:12
/
/
/
11:8
R/W
0x0
NDFC_READ_PIPE
In SDR mode:
0: Normal
1: EDO
2: E-EDO
Other : Reserved
In DDR mode:
1~15 is valid.(These bits configure the number of clock when data is valid
after RE#’s falling edge)
7:6
/
/
/
5:0
R/W
0x0
NDFC_DC_CTL
NDFC Delay Chain Control. (These bits are only valid in DDR data interface,
and configure the relative phase between DQS and DQ[0…7] )
5.2.6.5. NDFC Timing Configure Register(Default Value: 0x00000095)
Offset: 0x10
Register Name: NDFC_TIMING_CFG
Bit
R/W
Default/Hex
Description
31:20
/
/
/
19:18
R/W
0
T_WC
Write Cycle Time
0: 1*2T
1: 2*2T
2: 3*2T
3: 4*2T
17:16
R/W
0
T_CCS
Change Column Setup Time
0: 16*2T
1: 24*2T
2: 32*2T
3: 64*2T
15:14
R/W
0
T_CLHZ
CLE High to Output Hi-z
0: 2*2T
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