Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 367
1: 8*2T
2: 16*2T
3: 31*2T
13:12
R/W
0
T_CS
CE Setup Time
0: 2*2T
1: 8*2T
2: 16*2T
3: 31*2T
11
T_CDQSS
DQS Setup Time for data input start
0: 8*2T
1: 24*2T
10:8
R/W
0
T_CAD
Command, Address, Data Delay
000: 4*2T
001: 8*2T
010: 12*2T
011: 16*2T
100: 24*2T
101: 32*2T
110/111: 64*2T
7:6
R/W
0x2
T_RHW
RE# high to WE# low cycle number
00: 4*2T
01: 8*2T
10: 12*2T
11: 20*2T
5:4
R/W
0x1
T_WHR
WE# high to RE# low cycle number
00: 8*2T
01: 16*2T
10: 24*2T
11: 32*2T
3:2
R/W
0x1
T_ADL
Address to Data Loading cycle number
00: 0*2T
01: 8*2T
10: 16*2T
11: 24*2T
1:0
R/W
0x1
T_WB
WE# high to busy cycle number
00:14*2T
01:22*2T
10: 30*2T
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