Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 368
11:38*2T
5.2.6.6. NDFC Address Low Word Register(Default Value: 0x00000000)
Offset: 0x14
Register Name: NDFC_ADDR_LOW
Bit
R/W
Default/Hex
Description
31:24
R/W
0
ADDR_DATA4
NAND Flash 4th Cycle Address Data
23:16
R/W
0
ADDR_DATA3
NAND Flash 3rd Cycle Address Data
15:8
R/W
0
ADDR_DATA2
NAND Flash 2nd Cycle Address Data
7:0
R/W
0
ADDR_DATA1
NAND Flash 1st Cycle Address Data
5.2.6.7. NDFC Address High Word Register(Default Value: 0x00000000)
Offset: 0x18
Register Name: NDFC_ADDR_HIGH
Bit
R/W
Default/Hex
Description
31:24
R/W
0
ADDR_DATA8
NAND Flash 8th Cycle Address Data
23:16
R/W
0
ADDR_DATA7
NAND Flash 7th Cycle Address Data
15:8
R/W
0
ADDR_DATA6
NAND Flash 6th Cycle Address Data
7:0
R/W
0
ADDR_DATA5
NAND Flash 5th Cycle Address Data
5.2.6.8. NDFC Data Block Number Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: NDFC_DATA_BLOCK_NUM
Bit
R/W
Default/Hex
Description
31:6
/
/
/
4:0
R/W
0
NDFC_DATA_BLOCK_NUM
DATA BLOCK Number
It is used for batch command procession.
0: no data
1: 1 data blocks
2: 2 data blocks
…
16: 16 data blocks
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