Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 371
This command will be sent to external Flash by NDFC.
5.2.6.11. NDFC Command Set Register 0(Default Value: 0x00E00530)
Offset: 0x28
Register Name: NDFC_CMD_SET0
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:16
R/W
0xE0
NDFC_RANDOM_READ_CMD1
Used for Batch Read Operation
15:8
R/W
0x05
NDFC_RANDOM_READ_CMD0
Used for Batch Read Operation
7:0
R/W
0x30
NDFC_READ_CMD
Used for Batch Read Operation
5.2.6.12. NDFC Command Set Register 1(Default Value: 0x70008510)
Offset: 0x2C
Register Name: NDFC_CMD_SET1
Bit
R/W
Default/Hex
Description
31:16
R/W
0x70
NDFC_READ_CMD0
Used for EF-NAND Page Read operation
23:16
R/W
0x00
NDFC_READ_CMD1
Used for EF-NAND Page Read operation
15:8
R/W
0x85
NDFC_RANDOM_WRITE_CMD
Used for Batch Write Operation
7:0
R/W
0x10
NDFC_PROGRAM_CMD
Used for Batch Write Operation
5.2.6.13. NDFC IO Data Register(Default Value: 0x00000000)
Offset: 0x30
Register Name: NDFC_IO_DATA
Bit
R/W
Default/Hex
Description
31:0
R/W
0
NDFC_IO_DATA
Read/ Write data into internal RAM
Access unit is 32-bit.
5.2.6.14. NDFC ECC Control Register(Default Value: 0x4a800008)
Offset: 0x34
Register Name: NDFC_ECC_CTL
Bit
R/W
Default/Hex
Description
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