Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 374
(i=0~3)
ECC Corrected Bits Number for ECC Data Block[n] (n from 0 to 3)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits
…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes
5.2.6.18. NDFC Error Counter Register 1(Default Value: 0x00000000)
Offset: 0x44
Register Name: NDFC_ERR_CNT1
Bit
R/W
Default/Hex
Description
[8i+7:8i]
(i=0~3)
R
0
ECC_COR_NUM
ECC Corrected Bits Number for ECC Data Block[n] (n from 4 to 7)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits
…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes
5.2.6.19. NDFC Error Counter Register 2(Default Value: 0x00000000)
Offset: 0x48
Register Name: NDFC_ERR_CNT2
Bit
R/W
Default/Hex
Description
[8i+7:8i]
(i=0~3)
R
0
ECC_COR_NUM
ECC Corrected Bits Number for ECC Data Block[n] (n from 8 to 11)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits
…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes
5.2.6.20. NDFC Error Counter Register 3(Default Value: 0x00000000)
Offset: 0x4C
Register Name: NDFC_ERR_CNT3
Bit
R/W
Default/Hex
Description
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