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Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 375
[8i+7:8i]
(i=0~3)
R
0
ECC_COR_NUM
ECC Corrected Bits Number for ECC Data Block[n] (n from 12 to 15)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits
…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes
5.2.6.21. NDFC User Data Register [n]( Default Value: 0xffffffff)
Offset: 0x50 + 0x4*n
Register Name: NDFC_USER_DATAn
Bit
R/W
Default/Hex
Description
31:0
R/W
0xffffffff
USER_DATA
User Data for ECC Data Block[n] (n from 0 to 15)
Notes: 1 ECC Data Block = 512 or 1024 bytes
Notes: n from 0 to 15
5.2.6.22. NDFC EFNAND STATUS Register(Default Value: 0x00000000)
Offset: 0x90
Register Name: NDFC_EFNAND_STATUS
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R
0x0
EF_NAND_STATUS
The Status Value for EF-NAND Page Read operation
5.2.6.23. NDFC Spare Area Register(Default Value: 0x00000400)
Offset: 0xA0
Register Name: NDFC_SPARE_AREA
Bit
R/W
Default/Hex
Description
31:16
/
/
/
15:0
R/W
0x400
NDFC_SPARE_ADR
This value indicates the spare area first byte address for NDFC interleave
page operation.
5.2.6.24. NDFC Pattern ID Register(Default Value: 0x00000000)
Offset: 0xA4
Register Name: NDFC_PAT_ID
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