Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 376
Bit
R/W
Default/Hex
Description
[2i+1:2i]
(i=0~15)
R
0
PAT_ID
Special Pattern ID for 16 ECC data block
0: All 0x00 is found
1: All 0xFF is found
Others: Reserved
5.2.6.25. NDFC Read Data Status Control Register(Default Value: 0x01000000)
Offset: 0xA8
Register Name: NDFC_RDATA_STA_CTL
Bit
R/W
Default/Hex
Description
31:25
/
/
/
24
R/W
1
NDFC_RDATA_STA_EN
0: Disable to count the number of bit 1 and bit 0 during current read
operation;
1: Enable to count the number of bit 1 and bit 0 during current read
operation;
The number of bit 1 and bit 0 during current read operation can be used to
check whether a page is blank or bad.
23:18
/
/
/
17:0
R/W
0
NDFC_RDATA_STA_TH
The threshold value to generate data status.
If the number of bit 1 during current read operation is less than or equal to
threshold value, the bit 13 of NDFC_ST register will be set.
If the number of bit 0 during current read operation is less than or equal to
threshold value, the bit 12 of NDFC_ST register will be set.
5.2.6.26. NDFC Read Data Status Register 0(Default Value: 0x00000000)
Offset: 0xAC
Register Name: NDFC_RDATA_STA_0
Bit
R/W
Default/Hex
Description
31:0
R
0
BIT_CNT_1
The number of input bit 1 during current command. It will be cleared
automatically when next command is executed.
5.2.6.27. NDFC Read Data Status Register 1(Default Value: 0x00000000)
Offset: 0xB0
Register Name: NDFC_RDATA_STA_1
Bit
R/W
Default/Hex
Description
31:0
R
0
BIT_CNT_0
The number of input bit 0 during current command. It will be cleared
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