Owners manual

Memory

Figure 5-17. SD/MMC Pin Diagram

5.3.5. Internal DMA Controller Description

SD/MMC controller has an internal DMA controller (IDMAC) to transfer data between host memory and SDMMC port.

With a descriptor, IDMAC can efficiently move data from source to destination by automatically loading next DMA

transfer arguments, which need less CPU intervention. Before transfer data in IDMAC, host driver should construct a

descriptor list, configure arguments of every DMA transfer, then launch the descriptor and start the DMA. IDMAC has an

interrupt controller, when enabled, it can interrupt the HOST CPU in situations such as data transmission completed or

some errors happened.

5.3.5.1. IDMAC Descriptor Structure

The IDMAC uses a descriptor with a chain structure, and each descriptor points to a unique buffer and the next

descriptor.

This figure illustrates the internal formats of a descriptor. The descriptor addresses must be aligned to the bus width

used for 32-bit buses. Each descriptor contains 16 bytes of control and status information.

confidential