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Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 382
5.3.5.3. DES1 definition
Bits
Name
Descriptor
31:16
/
/
15:0
Buffer size
BUFF_SIZE
These bits indicate the data buffer byte size, which must be a multiple
of 4 bytes. If this filed is 0, the DMA ignores this buffer and proceeds to
the next descriptor.
5.3.5.4. DES2 definition
Bits
Name
Descriptor
31:0
Buffer address pointer
BUFF_ADDR
These bits indicate the physical address of data buffer. The IDMAC
ignores DES2[1:0], corresponding to the bus width of 32.
5.3.5.5. DES3 definition
Bits
Name
Descriptor
31:0
Next descriptor address
NEXT_DESP_ADDR
These bits indicate the pointer to the physical memory where the next
descriptor is present.
5.3.6. SD/MMC Register List
Module Name
Base Address
SD/MMC0
0x01C0F000
SD/MMC1
0x01C10000
SD/MMC2
0x01C11000
Register Name
Offset
Description
SD_GCTL
0x00
Control register
SD_CKCR
0x04
Clock Control register
SD_TMOR
0x08
Time out register
SD_BWDR
0x0C
Bus Width register
SD_BKSR
0x10
Block size register
SD_BYCR
0x14
Byte count register
SD_CMDR
0x18
Command register
SD_CAGR
0x1C
Command argument register
SD_RESP0
0x20
Response 0 register
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