Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 383
SD_RESP1
0x24
Response 1 register
SD_RESP2
0x28
Response 2 register
SD_RESP3
0x2C
Response 3 register
SD_IMKR
0x30
Interrupt mask register
SD_MISR
0x34
Masked interrupt status register
SD_RISR
0x38
Raw interrupt status register
SD_STAR
0x3C
Status register
SD_FWLR
0x40
FIFO Water Level register
SD_FUNS
0x44
FIFO Function Select register
SD_A12A
0x58
Auto command 12 argument
SD_NTSR
0x5C
SD NewTiming Set Register
SD_SDBG
0x60
SD NewTiming Set Debug Register
SD_HWRST
0x78
Hardware Reset Register
SD_DMAC
0x80
BUS Mode Control
SD_DLBA
0x84
Descriptor List Base Address
SD_IDST
0x88
DMAC Status
SD_IDIE
0x8C
DMAC Interrupt Enable
SD_THLDC
0x100
Card Threshold Control register
SD_DSBD
0x10C
eMMC4.41 DDR Start Bit Detection Control
SD_RES_CRC
0x110
CRC status from card/eMMC in write operation
SD_DATA7_CRC
0x114
CRC Data7 from card/eMMC
SD_DATA6_CRC
0x118
CRC Data7 from card/eMMC
SD_DATA5_CRC
0x11C
CRC Data7 from card/eMMC
SD_DATA4_CRC
0x120
CRC Data7 from card/eMMC
SD_DATA3_CRC
0x124
CRC Data7 from card/eMMC
SD_DATA2_CRC
0x128
CRC Data7 from card/eMMC
SD_DATA1_CRC
0x12C
CRC Data7 from card/eMMC
SD_DATA0_CRC
0x130
CRC Data7 from card/eMMC
SD_CRC_STA
0x134
Response CRC from card/eMMC
SD_FIFO
0X200
Read/Write FIFO
5.3.7. SD/MMC Register Description
5.3.7.1. SD Global Control Register(Default Value: 0x00000300)
Offset: 0x0000
Register Name: SD_CTRL
Bit
R/W
Default/Hex
Description
31
R/W
0
FIFO_AC_MOD
FIFO Access Mode
1-AHB bus
0-DMA bus
30:11
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