Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 384
10
R/W
0
DDR_MOD_SEL
DDR Mode Select
0 – SDR mode
1 – DDR mode
9
-
-
reserved
8
R/W
1
CD_DBC_ENB
Card Detect (Data[3] status) De-bounce Enable
0 - disable de-bounce
1 – enable de-bounce
7:6
-
-
/
5
R/W
0
DMA_ENB
DMA Global Enable
0 – Disable DMA to transfer data, using AHB bus
1 – Enable DMA to transfer data
4
R/W
0
INT_ENB
Global Interrupt Enable
0 – Disable interrupts
1 – Enable interrupts
3
-
-
/
2
R/W
0
DMA_RST
DMA Reset
1
R/W
0
FIFO_RST
FIFO Reset
0 – No change
1 – Reset FIFO
This bit is auto-cleared after completion of reset operation.
0
R/W
0
SOFT_RST
Software Reset
0 – No change
1 – Reset SD/MMC controller
This bit is auto-cleared after completion of reset operation.
5.3.7.2. SD Clock Control Register(Default Value: 0x00000000)
Offset: 0x0004
Register Name: SD_CLKDIV
Bit
R/W
Default/Hex
Description
31
R/W
0
MASK_DATA0
0 - Do not mask data0 when updata clock ;
1 - Mask data0 when updata clock;
30:18
/
/
/
17
R/W
0
CCLK_CTRL
Card Clock Output Control
0 – Card clock always on
1 – Turn off card clock when FSM in IDLE state
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