Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 385
16
R/W
0
CCLK_ENB
Card Clock Enable
0 – Card Clock off
1 – Card Clock on
15:8
/
/
/
7:0
R/W
0
CCLK_DIV
Card clock divider
n – Source clock is divided by 2*n.(n=0~255)
5.3.7.3. SD Timeout Register (Default Value: 0xFFFFFF40)
Offset: 0x0008
Register Name: SD_TMOUT
Bit
R/W
Default/Hex
Description
31:8
R/W
0xffffff
DTO_LMT
Data Timeout Limit
7:0
R/W
0x40
RTO_LMT
Response Timeout Limit
5.3.7.4. SD Bus Width Register (Default Value: 0x00000000)
Offset: 0x000c
Register Name: SD_CTYPE
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1:0
R/W
0
CARD_WID
Card width
2’b00 – 1-bit width
2’b01 – 4-bit width
2’b1x – 8-bit width
5.3.7.5. SD Block Size Register (Default Value: 0x00000200)
Offset: 0x0010
Register Name: SD_BLKSIZ
Bit
R/W
Default/Hex
Description
31:16
/
/
/
15:0
R/W
0x200
BLK_SZ
Block size
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