Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 386
5.3.7.6. SD Block Count Register (Default Value: 0x00000200)
Offset: 0x0014
Register Name: SD_BYTCNT
Bit
R/W
Default/Hex
Description
31:0
R/W
0x200
BYTE_CNT
Byte counter
Number of bytes to be transferred; should be integer multiple of Block Size
for block transfers.
5.3.7.7. SD Command Register (Default Value: 0x00000000)
Offset: 0x0018
Register Name: SD_CMD
Bit
R/W
Default/Hex
Description
31
R/W
0
CMD_LOAD
Start Command.
This bit is auto cleared when current command is sent. If there is no any
response error happened, a command complete interrupt bit (CMD_OVER)
will be set in interrupt register. You should not write any other command
before this bit is cleared, or a command busy interrupt bit (CMD_BUSY) will
be set in interrupt register.
30
/
/
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29
R/W
0
Use Hold Register
0 - CMD and DATA sent to card bypassing HOLD Register
1 - CMD and DATA sent to card through the HOLD Register
28
R/W
0
VOL_SW
Voltage Switch
0 – normal command
1 – Voltage switch command, set for CMD11 only
27
R/W
0
BOOT_ABT
Boot Abort
Setting this bit will terminate the boot operation.
26
R/W
0
EXP_BOOT_ACK
Expect Boot Acknowledge.
When Software sets this bit along in mandatory boot operation, controller
expects a boot acknowledge start pattern of 0-1-0 from the selected card.
25:24
R/W
0
BOOT_MOD
Boot Mode
2’b00 – normal command
2’b01 - Mandatory Boot operation
2’b10 - Alternate Boot operation
2’b11 - reserved
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