Owners manual

Memory
H3 Datasheet(Revision1.2) Copyrigh 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 387
21
R/W
0
PRG_CLK
Change Clock
0 Normal command
1 Change Card Clock; when this bit is set, controller will change clock
domain and clock output. No command will be sent.
20:16
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15
R/W
0
SEND_INIT_SEQ
Send Initialization
0 normal command sending
1 Send initialization sequence before sending this command.
14
R/W
0
STOP_ABT_CMD
Stop Abort Command
0 normal command sending
1 send Stop or abort command to stop current data transfer in
progress.(CMD12, CMD52 for writing “I/O Abort” in SDIO CCCR)
13
R/W
0
WAIT_PRE_OVER
Wait Data Transfer Over
0 Send command at once, do not care of data transferring
1 Wait for data transfer completion before sending current command
12
R/W
0
STOP_CMD_FLAG
Send Stop CMD Automatically (CMD12)
0 Do not send stop command at end of data transfer
1 Send stop command automatically at end of data transfer
11
R/W
0
TRANS_MODE
Transfer Mode
0 Block data transfer command
1 Stream data transfer command
10
R/W
0
TRANS_DIR
Transfer Direction
0 Read operation
1 Write operation
9
R/W
0
DATA_TRANS
Data Transfer
0 without data transfer
1 with data transfer
8
R/W
0
CHK_RESP_CRC
Check Response CRC
0 Do not check response CRC
1 Check response CRC
7
R/W
0
LONG_RESP
Response Type
0 Short Response (48 bits)
1 Long Response (136 bits)
6
R/W
0
RESP_RCV
Response Receive
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