Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 390
31:0
R
0
MSKD_ISTA
Interrupt status. Enabled only if corresponding bit in mask register is set.
Bit field defined as following:
bit 31 – card removed
bit 30 – card inserted
bit 17~29 - reserved
bit 16 – SDIO interrupt
bit 15 – Data End-bit error
bit 14 – Auto command done
bit 13 – Data Start Error
bit 12 – Command Busy and illegal write
bit 11 – FIFO under run/overflow
bit 10 – Data starvation timeout (HTO)/V1.8 Switch Done
bit 9 – Data timeout/Boot data start
bit 8 – Response timeout/Boot ACK received
bit 7 – Data CRC error
bit 6 – Response CRC error
bit 5 – Data Receive Request
bit 4 –Data Transmit Request
bit 3 – Data Transfer Complete
bit 2 – Command Complete
bit 1 – Response Error (no response or response CRC error)
bit 0 – Reserved
5.3.7.15. SD Raw Interrupt Status Register (Default Value: 0x00000000)
Offset: 0x0038
Register Name: SD_RINTSTS
Bit
R/W
Default/Hex
Description
31:0
R/W
0
RAW_ISTA
Raw Interrupt Status.
This is write-1-to-clear bits.
Bit field defined as following:
bit 31 – card removed
bit 30 – card inserted
bit 17~29 - reserved
bit 16 – SDIO interrupt
bit 15 – Data End-bit error
bit 14 – Auto command done
bit 13 – Data Start Error
bit 12 – Command Busy and illegal write
bit 11 – FIFO under run/overflow
bit 10 – Data starvation timeout (HTO)/V1.8 Switch Done
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