Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 391
bit 9 – Data timeout/Boot data start
bit 8 – Response timeout/Boot ACK received
bit 7 – Data CRC error
bit 6 – Response CRC error
bit 5 – Data Receive Request
bit 4 –Data Transmit Request
bit 3 – Data Transfer Complete
bit 2 – Command Complete
bit 1 – Response Error (no response or response CRC error)
bit 0 – Reserved
5.3.7.16. SD Status Register (Default Value: 0x00000006)
Offset: 0x003C
Register Name: SD_STATUS
Bit
R/W
Default/Hex
Description
31
R
0
DMA_REQ
dma_req
DMA request signal state
30:22
/
/
/
21:17
R
0
FIFO_LEVEL
FIFO Level
Number of filled locations in FIFO
16:11
R
0
RESP_IDX
Response Index
Index of previous response, including any auto-stop sent by controller
10
R
0
FSM_BUSY
Data FSM Busy
Data transmit or receive state-machine is busy
9
R
0
CARD_BUSY
Card data busy
Inverted version of DATA[0]
0 – card data not busy
1 – card data busy
8
R
0
CARD_PRESENT
Data[3] status
level of DATA[3]; checks whether card is present
0 – card not present
1 – card present
7:4
R
0
FSM_STA
Command FSM states:
0 – Idle
1 – Send init sequence
2 – Tx cmd start bit
3 – Tx cmd tx bit
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