Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 392
4 – Tx cmd index + arg
5 – Tx cmd crc7
6 – Tx cmd end bit
7 – Rx resp start bit
8 – Rx resp IRQ response
9 – Rx resp tx bit
10 – Rx resp cmd idx
11 – Rx resp data
12 – Rx resp crc7
13 – Rx resp end bit
14 – Cmd path wait NCC
15 – Wait; CMD-to-response turnaround
3
R
0
FIFO_FULL
FIFO full
1 – FIFO full
0 – FIFO not full
2
R
1
FIFO_EMPTY
FIFO Empty
1 - FIFO Empty
0 - FIFO not Empty
1
R
1
FIFO_TX_LEVEL
FIFO TX Water Level flag
0 – FIFO didn’t reach transmit trigger level
1 - FIFO reached transmit trigger level
0
R
0
FIFO_RX_LEVEL
FIFO TX Water Level flag
0 – FIFO didn’t reach receive trigger level
1 - FIFO reached receive trigger level
5.3.7.17. SD FIFO Water Level Register (Default Value: 0x000F0000)
Offset: 0x0040
Register Name: SD_FIFOTH
Bit
R/W
Default/Hex
Description
31
/
/
/
30:28
R/W
0
BSIZE_OF_TRANS
Burst size of multiple transaction
000 – 1 transfers
001 – 4
010 – 8
011 – 16
100 – 32
101 – 64
110 – 128
111 – 256
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