Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 393
Should be programmed same as DMA controller multiple transaction size.
The units for transfers are the DWORD. A single transfer would be signaled
based on this value. Value should be sub-multiple of (RX_TL + 1) and
(FIFO_DEPTH - TX_TL)
Recommended:
MSize = 8, TX_TL = 16, RX_TL = 15
27:21
R
0
/
20:16
R/W
0xF
RX_TL
Rx Trigger Level
0x0~0x1e – RX Trigger Level is 0~30
0x1f – reserved
FIFO threshold when FIFO request host to receive data from FIFO. When
FIFO data level is greater than this value, DMA is request is raised if DMA
enabled, or RX interrupt bit is set if interrupt enabled. At the end of packet,
if the last transfer is less than this level, the value is ignored and relative
request will be raised as usual.
Recommended: 15 (means greater than 15)
15:5
R
0
/
4:0
R/W
0
TX_TL
TX Trigger Level
0x1~0xf – TX Trigger Level is 1~31
0x0 – no trigger
FIFO threshold when FIFO requests host to transmit data to FIFO. When FIFO
data level is less than or equal to this value, DMA TX request is raised if DMA
enabled, or TX request interrupt bit is set if interrupt enabled. At the end of
packet, if the last transfer is less than this level, the value is ignored and
relative request will be raised as usual.
Recommended: 16 (means less than or equal to 16)
5.3.7.18. SD Function Select Register (Default Value: 0x00000000)
Offset: 0x0044
Register Name: SD_CTRL
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2
R/W
0
ABT_RDATA
Abort Read Data
0 – Ignored
1– After suspend command is issued during read-transfer, software polls
card to find when suspend happened. Once suspend occurs, software
sets bit to reset data state-machine, which is waiting for next block of
data.
Used in SDIO card suspends sequence.
This bit is auto-cleared once controller reset to idle state.
1
R/W
0
READ_WAIT
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