Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 394
Read Wait
0 – Clear SDIO read wait
1 – Assert SDIO read wait
0
R/W
0
HOST_SEND_MMC_IRQRESQ
Host Send MMC IRQ Response
0 – Ignored
1 – Send auto IRQ response
When host is waiting MMC card interrupt response, setting this bit will
make controller cancel wait state and return to idle state, at which time,
controller will receive IRQ response sent by itself.
This bit is auto-cleared after response is sent.
5.3.7.19. SD Auto Command 12 Register (Default Value: 0x0000ffff)
Offset: 0x0058
Register Name: SD_A12A
Bit
R/W
Default/Hex
Description
31:16
/
/
/
0:15
R/W
0xffff
SD_A12A.
SD_A12A set the argument of command 12 automatically send by controller
5.3.7.20. SD NewTiming Set Register (Default Value: 0x00000001,only used in SDC1/2)
Offset: 0x005C
Register Name: SD_NTSR_REG
Bit
R/W
Default/Hex
Description
31
R/W
0
MODE_SELEC
0 - Old mode of Sample/Output Timing ;
1 - New mode of Sample/Output Timing;
Default : 0;
30:6
R/W
0x00
SAMPLE_TIMING_PHASE(RX)
00 - Sample timing phase offset 90。;
01 - Sample timing phase offset 180。;
10 - Sample timing phase offset 270。;
11 - Ignore;
Default : 00;
3:2
/
/
/
1:0
R/W
0x01
OUTPUT_TIMING_PHASE(TX)
00 - Output timing phase offset 90。;
01 - Output timing phase offset 180。;
10 - Output timing phase offset 270。;
11 - Ignore;
Default : 01;
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