Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 395
5.3.7.21. SD Hardware Reset Register (Default Value: 0x00000001)
Offset: 0x0078
Register Name: SD_HWRST
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
1
HW_RESET.
1 – Active mode
0 – Reset
These bits cause the cards to enter pre-idle state, which requires them to be
re-initialized.
5.3.7.22. SD DMAC Control Register (Default Value: 0x00000000)
Offset: 0x0080
Register Name: SD_BUS_MODE
Bit
R/W
Default/Hex
Description
31
W
0
DES_LOAD_CTRL
When DMAC fetches a descriptor, if the valid bit of a descriptor is not set,
DMAC FSM will go to the suspend state. Setting this bit will make DMAC
re-fetch descriptor again and do the transfer normally.
30:11
/
/
/
10:8
R
0
PRG_BURST_LEN
Programmable Burst Length.
These bits indicate the maximum number of beats to be performed in one
IDMAC transaction. The IDMAC will always attempt to burst as specified in
PBL each time it starts a Burst transfer on the host bus. The permissible
values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE
of FIFOTH register. In order to change this value, write the required value to
FIFOTH register. This is an encode value as follows.
000 – 1 transfers
001 – 4 transfers
010 – 8 transfers
011 – 16 transfers
100 – 32 transfers
101 – 64 transfers
110 – 128 transfers
111 – 256 transfers
Transfer unit is either 16, 32, or 64 bits, based on HDATA_WIDTH. PBL is a
read-only value.
7
R/W
0
IDMAC_ENB
IDMAC Enable.
When set, the IDMAC is enabled. DE is read/write.
6:2
R/W
0
DES_SKIP_LEN
Descriptor Skip Length.
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