Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 396
Specifies the number of Word to skip between two unchained descriptors.
This is applicable only for dual buffer structure.
Default is set to 4 DWORD.
1
R/W
0
FIX_BUST_CTRL
Fixed Burst.
Controls whether the AHB Master interface performs fixed burst transfers or
not. When set, the AHB will use only SINGLE, INCR4, INCR8 during start of
normal burst transfers. When reset, the AHB will use SINGLE and INCR burst
transfer operations.
0
R/W
0
IDMAC_RST
DMA Reset.
When set, the DMA Controller resets all its internal registers. SWR is
read/write. It is automatically cleared after 1 clock cycle.
5.3.7.23. SD Descriptor List Base Address Register (Default Value: 0x00000000)
Offset: 0x0084
Register Name: SD_DLBA
Bit
R/W
Default/Hex
Description
31:0
R/W
0
DES_BASE_ADDR
Start of Descriptor List.
Contains the base address of the First Descriptor. The LSB bits [1:0] are
ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits
are read-only.
5.3.7.24. SD DMAC Status Register (Default Value: 0x0000_0000)
Offset: 0x0088
Register Name: SD_DSR
Bit
R/W
Default/Hex
Description
31:17
/
/
/
16:13
R
0
DMAC_FSM_STA
DMAC FSM present state.
0 – DMA_IDLE
1 – DMA_SUSPEND
2 – DESC_RD
3 – DESC_CHK
4 – DMA_RD_REQ_WAIT
5 – DMA_WR_REQ_WAIT
6 – DMA_RD
7 – DMA_WR
8 – DESC_CLOSE
This bit is read-only.
12:10
R
0
DMAC_ERR_STA
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