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Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 398
1
R/W
0
RX_INT
Receive Interrupt.
Indicates the completion of data reception for a descriptor. Writing a 1
clears this bit.
0
R/W
0
TX_INT
Transmit Interrupt.
Indicates that data transmission is finished for a descriptor. Writing a ‘1’
clears this bit.
5.3.7.25. SD DMAC Interrupt Enable Register (Default Value: 0x00000000)
Offset: 0x008C
Register Name: SD_IDIE_REG
Bit
R/W
Default/Hex
Description
31:10
/
/
/
9
R/W
0
ABN_INT_ENB
Abnormal Interrupt Summary Enable.
When set, an abnormal interrupt is enabled. This bit enables the following
bits:
IDINTEN[2] – Fatal Bus Error Interrupt
IDINTEN[4] – DU Interrupt
IDINTEN[5] – Card Error Summary Interrupt
8
R/W
0
NOR_INT_ENB
Normal Interrupt Summary Enable.
When set, a normal interrupt is enabled. When reset, a normal interrupt is
disabled. This bit enables the following bits:
IDINTEN[0] – Transmit Interrupt
IDINTEN[1] – Receive Interrupt
7:6
/
/
/
5
R/W
0
ERR_SUM_INT_ENB
Card Error summary Interrupt Enable.
When set, it enables the Card Interrupt summary.
4
R/W
0
DES_UNAVL_INT_ENB
Descriptor Unavailable Interrupt.
When set along with Abnormal Interrupt Summary Enable, the DU interrupt
is enabled.
3
/
/
/
2
R/W
0
FERR_INT_ENB
Fatal Bus Error Enable.
When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error
Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
disabled.
1
R/W
0
RX_INT_ENB
Receive Interrupt Enable.
When set with Normal Interrupt Summary Enable, Receive Interrupt is
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