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Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 399
enabled. When reset, Receive Interrupt is disabled.
0
R/W
0
TX_INT_ENB
Transmit Interrupt Enable.
When set with Normal Interrupt Summary Enable, Transmit Interrupt is
enabled. When reset, Transmit Interrupt is disabled.
5.3.7.26. Card Threshold Control Register (Default Value: 0x00000000)
Offset: 0x0100
Register Name: SD_THLD_REG
Bit
R/W
Default/Hex
Description
31:28
/
/
/
27:16
R/W
0
CARD_RD_THLD
Card Read Threshold Size
15:1
/
/
/
0
R/W
0
CARD_RD_THLD_ENB
Card Read Threshold Enable
0 – Card Read Threshold Disable
1 - Card Read Threshold Enable
Host controller initiates Read Transfer only if CARD_RD_THLD amount of
space is available in receive FIFO
5.3.7.27. eMMC4.41 DDR Start Bit Detection Control Register (Default Value: 0x00000000)
Offset: 0x010C
Register Name: EMMC_DDR_SBIT_DET_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0
HALF_START_BIT
Control for start bit detection mechanism inside mstorage based on
duration of start bit.
For eMMC 4.41, start bit can be:
0 - Full cycle
1 - Less than one full cycle
Set HALF_START_BIT=1 for eMMC 4.41 and above; set to 0 for SD
applications.
5.3.7.28. SD Response CRC Register (Default Value: 0x00000000)
Offset: 0x0110
Register Name: RESP_CRC_REG
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6:0
R
0
RESP_CRC
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