Owners manual

Image
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 405
6.1.2.2. CSI FIFO Distribution
Interface
YUYV422 Interleaved/Raw
BT656 Interface
Input format
YUV422
Raw
YUV422
Output format
Planar
UV combined/ MB
Raw/RGB/PRGB
Planar
UV combined/MB
CH0_FIFO0
Y pixel data
Y pixel data
All pixels data
Y
Y
CH0_FIFO1
Cb (U) pixel data
Cb (U) Cr (V)
pixel data
-
Cb (U)
CbCr (UV)
CH0_FIFO2
Cr (V) pixel data
-
-
Cr (V)
6.1.2.3. CSI Timing
VSYNC
HSYNC
DATA
HSYNC
DATA[7/9/11:0]
PCLK
n frame n+1 frame
…
first line second line last line
…
…
…
Figure 6-3. 8/10/12-bit CMOS Sensor Interface Timing
(clock rising edge sample.vsync valid = positive,hsycn valid = positive)
PCLK
D[7:0]
Cb0
[7:0]
Y0
[7:0]
Cr0
[7:0]
Y1
[7:0]
Cb2
[7:0]
Y2
[7:0]
Cr2
[7:0]
...
SAV
blank
Pixel0~Pixel1
Pixel2~Pixel3
...
FF
00 00 XY
FF
Y3
[7:0]
Figure 6-4. 8-bit YCbCr4:2:2 with embedded syncs(BT656) Timing
confidential