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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 406
6.1.2.4. Bit Definition
CCIR656 Header Data Bit Definition:
Data Bit
First Word(0xFF)
Second Word(0x00)
Third Word(0x00)
Fourth Word
CS D[9] (MSB)
1
0
0
1
CS D[8]
1
0
0
F
CS D[7]
1
0
0
V
CS D[6]
1
0
0
H
CS D[5]
1
0
0
P3
CS D[4]
1
0
0
P2
CS D[3]
1
0
0
P1
CS D[2]
1
0
0
P0
CS D[1]
x
x
x
x
CS D[0]
x
x
x
x
Note: For compatibility with 8-bit interface, CS D[1] and CS D[0] are not defined.
Decode
F
V
H
P3
P2
P1
P0
Field 1 start of active video (SAV)
0
0
0
0
0
0
0
Field 1 end of active video (EAV)
0
0
1
1
1
0
1
Field 1 SAV (digital blanking)
0
1
0
1
0
1
1
Field 1 EAV (digital blanking)
0
1
1
0
1
1
0
Field 2 SAV
1
0
0
0
1
1
1
Field 2 EAV
1
0
1
1
0
1
0
Field 2 SAV (digital blanking)
1
1
0
1
1
0
0
Field 2 EAV (digital blanking)
1
1
1
0
0
0
1
6.1.3. Register list
Module Name
Base Address
CSI0
0x01CB0000
Register Name
Offset
Register name
CSI0_EN_REG
0X0000
CSI Enable register
CSI0_IF_CFG_REG
0X0004
CSI Interface Configuration Register
CSI0_CAP_REG
0X0008
CSI Capture Register
CSI0_SYNC_CNT_REG
0X000C
CSI Synchronization Counter Register
CSI0_FIFO_THRS_REG
0X0010
CSI FIFO Threshold Register
CSI0_PTN_LEN_REG
0X0030
CSI Pattern Generation Length register
CSI0_PTN_ADDR_REG
0X0034
CSI Pattern Generation Address register
CSI0_VER_REG
0X003C
CSI Version Register
CSI0_C0_CFG_REG
0X0044
CSI Channel_0 configuration register
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