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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 407
CSI0_C0_SCALE_REG
0X004C
CSI Channel_0 scale register
CSI0_C0_F0_BUFA_REG
0X0050
CSI Channel_0 FIFO 0 output buffer-A address register
CSI0_C0_F1_BUFA_REG
0X0058
CSI Channel_0 FIFO 1 output buffer-A address register
CSI0_C0_F2_BUFA_REG
0X0060
CSI Channel_0 FIFO 2 output buffer-A address register
CSI0_C0_CAP_STA_REG
0X006C
CSI Channel_0 status register
CSI0_C0_INT_EN_REG
0X0070
CSI Channel_0 interrupt enable register
CSI0_C0_INT_STA_REG
0X0074
CSI Channel_0 interrupt status register
CSI0_C0_HSIZE_REG
0X0080
CSI Channel_0 horizontal size register
CSI0_C0_VSIZE_REG
0X0084
CSI Channel_0 vertical size register
CSI0_C0_BUF_LEN_REG
0X0088
CSI Channel_0 line buffer length register
CSI0_C0_FLIP_SIZE_REG
0X008C
CSI Channel_0 flip size register
CSI0_C0_FRM_CLK_CNT_REG
0X0090
CSI Channel_0 frame clock counter register
CSI0_C0_ACC_ITNL_CLK_CNT_REG
0X0094
CSI Channel_0 accumulated and internal clock counter register
CSI0_C0_FIFO_STAT_REG
0X0098
CSI Channel_0 FIFO Statistic Register
CSI0_C0_PCLK_STAT_REG
0X009C
CSI Channel_0 PCLK Statistic Register
CCI_CTRL
0x3000
CCI control register
CCI_CFG
0x3004
CCI transmission config register
CCI_FMT
0x3008
CCI packet format register
CCI_BUS_CTRL
0x300C
CCI bus control register
CCI_INT_CTRL
0x3014
CCI interrupt control register
CCI_LC_TRIG
0x3018
CCI line counter trigger register
CCI_FIFO_ACC
0x3100
CCI FIFO access register
CCI_RSV_REG
0x3200
CCI reserved register
6.1.4. Register Description
6.1.4.1. CSI Enable Register (Default Value: 0x00000000)
Offset: 0x0000
Register Name: CSI0_EN_REG
Bit
R/W
Default/Hex
Description
31
/
/
/
30
R/W
0x0
VER_EN
CSI Version Register Read Enable:
0: Disable
1: Enable
29:24
/
/
/
23:16
R/W
0x00
PTN_CYCLE
Pattern generating cycle counter.
The pattern in dram will be generated in cycles of PTN_CYCLE+1.
15:9
/
/
/
8
R/W
0x0
SRAM_PWDN
0: SRAM in normal
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