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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 408
1: SRAM in power down
7:5
/
/
/
4
R/W
0x0
PTN_START
CSI Pattern Generating Start
0: Finish
other: Start
Software write this bit to“1” to start pattern generating from DRAM. When
finished, the hardware will clear this bit to“0”automatically. Generating
cycles depends on PTN_CYCLE.
3
R/W
0
CLK_CNT_SPL
Sampling time for clk counter per frame
0: Sampling clock counter every frame done
1: Sampling clock counter every vsync
2
R/W
0
CLK_CNT_EN
clk count per frame enable
1
R/W
0
PTN_GEN_EN
Pattern Generation Enable
0
R/W
0
CSI_EN
Enable
0: Reset and disable the CSI module
1: Enable the CSI module
6.1.4.2. CSI Interface Configuration Register (Default Value: 0x00000000)
Offset: 0x0004
Register Name: CSI0_IF_CFG_REG
Bit
R/W
Default/Hex
Description
31:22
/
/
/
21
R/W
0
SRC_TYPE
Source type
0: Progressed
1: Interlaced
20
R/W
0
FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
19
R/W
0
FIELD
For YUV HV timing, Field polarity
0: negative(field=0 indicate odd, field=1 indicate even )
1: positive(field=1 indicate odd, field=0 indicate even )
For BT656 timing, Field sequence
0: Normal sequence (field 0 first)
1: Inverse sequence (field 1 first)
18
R/W
1
VREF_POL
Vref polarity
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