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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 409
0: negative
1: positive
This register is not apply to CCIR656 interface.
17
R/W
0
HERF_POL
Href polarity
0: negative
1: positive
This register is not apply to CCIR656 interface.
16
R/W
1
CLK_POL
Data clock type
0: active in rising edge
1: active in falling edge
15:12
/
/
/
11:10
R/W
0
SEQ_8PLUS2
When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at
CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual csi data bus
according to these sequences:
00: 6’bx+D[9:8], D[7:0]
01: D[9:2], 6’bx+D[1:0]
10: D[7:0], D[9:8]+6’bx
11: D[7:0], 6’bx+D[9:8]
9:8
R/W
0
IF_DATA_WIDTH
00: 8 bit data bus
01: 10 bit data bus
10: 12 bit data bus
11: 8+2bit data bus
7:5
/
/
/
4:0
R/W
0
CSI_IF
YUV:
00000: YUYV422 Interleaved or RAW (All data in one data bus)
CCIR656:
00100: YUYV422 Interleaved or RAW (All data in one data bus)
Others: Reserved
6.1.4.3. CSI Capture Register (Default Value: 0x00000000)
Offset: 0x0008
Register Name: CSI0_CAP_REG
Bit
R/W
Default/Hex
Description
31:6
/
/
/
5:2
R/W
0x0
CH0_CAP_MASK
Vsync number masked before capture.
1
R/W
0x0
CH0_VCAP_ON
Video capture control: Capture the video image data stream on channel 0.
0: Disable video capture
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