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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 410
If video capture is in progress, the CSI stops capturing image data at the end
of the current frame, and all of the current frame data is wrote to output
FIFO.
1: Enable video capture
The CSI starts capturing image data at the start of the next frame.
0
R/W
0x0
CH0_SCAP_ON
Still capture control: Capture a single still image frame on channel 0.
0: Disable still capture.
1: Enable still capture
The CSI module starts capturing image data at the start of the next frame.
The CSI module captures only one frame of image data. This bit is self
clearing and always reads as a 0.
6.1.4.4. CSI Synchronization Counter Register (Default Value: 0x00000000)
Offset: 0x000C
Register Name: CSI0_SYNC_CNT_REG
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:0
R
0
SYNC_CNT
The counter value between vsync of CSI0 channel 0 and vsync of CSI1
channel 0 , using 24MHz.
6.1.4.5. CSI FIFO Threshold Register (Default Value: 0x040f0400)
Offset: 0x0010
Register Name: CSI0_FIFO_THRS_REG
Bit
R/W
Default/Hex
Description
31:29
/
/
/
28:26
R/W
0x1
FIFO_NEARLY_FULL_TH
The threshold of FIFO being nearly full. Indicates that the ISP should stop
writing. Only valid when ISP is enabled.
0~7:
The smaller the value, the flag of FIFO being nearly full is easier to reach.
25:24
R/W
0x0
PTN_GEN_CLK_DIV
Packet generator clock divider
23:16
R/W
0x0f
PTN_GEN_DLY
Clocks delayed before pattern generating start.
15:12
/
/
/
11:00
R/W
0x400
FIFO_THRS
When CSI0 FIFO occupied memory exceed the threshold, dram frequency
can not change.
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