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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 415
01
R
0
VCAP_STA
Video capture in progress
Indicates the CSI is capturing video image data (multiple frames). The bit is
set at the start of the first frame after enabling video capture. When
software disables video capture, it clears itself after the last pixel of the
current frame is captured.
00
R
0
SCAP_STA
Still capture in progress
Indicates the CSI is capturing still image data (single frame). The bit is set at
the start of the first frame after enabling still frame capture. It clears itself
after the last pixel of the first frame is captured.
For CCIR656 interface, if the output format is frame planar YCbCr 420 mode,
the frame end means the field2 end, the other frame end means filed end.
6.1.4.15. CSI Channel_0 interrupt enable Register (Default Value: 0x00000000)
Offset: 0x0070
Register Name: CSI0_C0_INT_EN_REG
Bit
R/W
Default/Hex
Description
31:08
/
/
/
07
R/W
0
VS_INT_EN
vsync flag
The bit is set when vsync come. And at this time load the buffer address for
the coming frame. So after this irq come, change the buffer address could
only effect next frame
06
R/W
0
HB_OF_INT_EN
Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.
05
R/W
0
MUL_ERR_INT_EN
Multi-channel writing error
Indicates error has been detected for writing data to a wrong channel.
04
R/W
0
FIFO2_OF_INT_EN
FIFO 2 overflow
The bit is set when the FIFO 2 become overflow.
03
R/W
0
FIFO1_OF_INT_EN
FIFO 1 overflow
The bit is set when the FIFO 1 become overflow.
02
R/W
0
FIFO0_OF_INT_EN
FIFO 0 overflow
The bit is set when the FIFO 0 become overflow.
01
R/W
0
FD_INT_EN
Frame done
Indicates the CSI has finished capturing an image frame. Applies to video
capture mode. The bit is set after each completed frame capturing data is
wrote to buffer as long as video capture remains enabled.
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