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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 416
00
R/W
0
CD_INT_EN
Capture done
Indicates the CSI has completed capturing the image data.
For still capture, the bit is set when one frame data has been wrote to
buffer.
For video capture, the bit is set when the last frame has been wrote to
buffer after video capture has been disabled.
For CCIR656 interface, if the output format is frame planar YCbCr 420 mode,
the frame end means the field2 end, the other frame end means field end.
6.1.4.16. CSI Channel_0 interrupt status Register (Default Value: 0x00000000)
Offset: 0x0074
Register Name: CSI0_C0_INT_STA_REG
Bit
R/W
Default/Hex
Description
31:08
/
/
/
07
R/W
0
VS_PD
vsync flag
06
R/W
0
HB_OF_PD
Hblank FIFO overflow
05
R/W
0
MUL_ ERR_PD
Multi-channel writing error
04
R/W
0
FIFO2_OF_PD
FIFO 2 overflow
03
R/W
0
FIFO1_OF_PD
FIFO 1 overflow
02
R/W
0
FIFO0_OF_PD
FIFO 0 overflow
01
R/W
0
FD_PD
Frame done
00
R/W
0
CD_PD
Capture done
6.1.4.17. CSI Channel_0 horizontal size Register (Default Value: 0x05000000)
Offset: 0x0080
Register Name: CSI0_C0_INT_STA_REG
Bit
R/W
Default/Hex
Description
31:29
/
/
/
28:16
R/W
500
HOR_LEN
Horizontal pixel unit length. Valid pixel of a line.
15:13
/
/
/
12:00
R/W
0
HOR_START
Horizontal pixel unit start. Pixel is valid from this pixel.
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