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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 418
23:00
R
0
FRM_CLK_CNT
Counter value between every frame. For instant hardware frame rate
statics.
The internal counter is added by one every 24MHz clock cycle. When frame
done or vsync comes, the internal counter value is sampled to
FRM_CLK_CNT, and cleared to 0.
6.1.4.22. CSI Channel_0 accumulated and internal clock counter Register (Default Value: 0x00000000)
Offset: 0x0094
Register Name: CSI0_C0_ACC_ITNL_CLK_CNT_REG
Bit
R/W
Default/Hex
Description
31:24
R
0
ACC_CLK_CNT
The accumulated value of FRM_CLK_CNT for software frame rate statics.
Every interrupt of frame done, the software check this accumulated value
and clear it to 0. If the ACC_CLK_CNT is larger than 1, the software has lost
frame.
When frame done or vsync comes, ACC_CLK_CNT = ACC_CLK_CNT + 1, and
cleared to 0 when writing 0 to this register.
23:00
R
0
ITNL_CLK_CNT
The instant value of internal frame clock counter.
When frame done interrupt comes, the software can query this counter for
judging whether it is the time for updating the double buffer address
registers.
6.1.4.23. CSI Channel_0 FIFO Statistic Register (Default Value: 0x00000000)
Offset: 0x0098
Register Name: CSI0_C0_FIFO_STAT_REG
Bit
R/W
Default/Hex
Description
31:12
/
/
/
11:00
R
0
FIFO_FRM_MAX
Indicates the maximum depth of FIFO being occupied for whole frame.
Update at every vsync or framedone.
6.1.4.24. CSI Channel_0 PCLK Statistic Register (Default Value: 0x00007FFF)
Offset: 0x009C
Register Name: CSI0_C0_PCLK_STAT_REG
Bit
R/W
Default/Hex
Description
31
/
/
/
30:16
R
0
PCLK_CNT_LINE_MAX
Indicates maximum pixel clock counter value for each line.
Update at every vsync or framedone.
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