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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 419
15
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14:00
R
0x7fff
PCLK_CNT_LINE_MIN
Indicates minimum pixel clock counter value for each line.
Update at every vsync or framedone.
6.1.4.25. CCI Control Register (Default Value: 0x00000000)
Offset: 0x3000
Register Name: CCI_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0
SINGLE_TRAN
0: Transmission idle
1: Start single transmission
Automatically cleared to ‘0’ when finished. Abort current transmission
immediately if changing from ‘1’ to ‘0’. If slave not respond for the expected
status over the time defined by TIMEOUT, current transmission will stop.
PACKET_CNT will return the sequence number when transmission fail. All
format setting and data will be loaded from registers and FIFO when
transmission start.
30
R/W
0
REPEAT_TRAN
0: transmission idle
1: repeated transmission
When this bit is set to 1, transmission repeats when trigger signal (such as
VSYNC/ VCAP done ) repeats.
If changing this bit from ‘1’ to ‘0’ during transmission, the current
transmission will be guaranteed then stop.
29
R/W
0
RESTART_MODE
0: RESTART
1: STOP+START
Define the CCI action after sending register address.
28
R/W
0
READ_TRAN_MODE
0: send slave_id+W
1: do not send slave_id+W
Note:Setting this bit to 1 if reading from a slave which register width is
equal to 0.
27:24
R
0
TRAN_RESULT
000: OK
001: FAIL
Other: Reserved
23:16
R
/
CCI_STA
0x00: bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
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