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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 420
0x28: Data byte transmitted in master mode, ACK received
0x30: Data byte transmitted in master mode, ACK not received
0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK received
0x58: Data byte received in master mode, ACK not received
0x01: Timeout when sending 9th SCL clk
Other: Reserved
15:2
/
/
/
1
R/W
0
SOFT_RESET
0: normal
1: reset
0
R/W
0
CCI_EN
0: Module disable
1: Module enable
6.1.4.26. CCI Transmission Configuration Register (Default Value: 0x10000000)
Offset: 0x3004
Register Name: CCI_CFG_REG
Bit
R/W
Default/Hex
Description
31:24
R/W
0x10
TIMEOUT_N
When sending the 9th clock, assert fail signal when slave device did not
response after N*FSCL cycles. And software must do a reset to CCI module
and send a stop condition to slave.
23:16
R/W
0x00
INTERVAL
Define the interval between each packet in 40*FSCL cycles. 0~255
15
R/W
0
PACKET_MODE
Select where to load slave id / data width
0: Compact mode
1: Complete mode
In compact mode, slave id/register width / data width will be loaded from
CCI_FMT register, only address and data read from memory.
In complete mode, they will be loaded from packet memory.
14:7
/
/
/
6:4
R/W
0
TRIG_MODE
Transmit mode:
000: Immediately, no trigger
001: Reserved
010: CSI0 int trigger
011: CSI1 int trigger
3:0
R/W
0
CSI_TRIG
CSI Int trig signal select:
0000: First HREF start
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