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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 421
0001: Last HREF done
0010: Line counter trigger
other: Reserved
6.1.4.27. CCI Packet Format Register (Default Value: 0x00110001)
Offset: 0x3008
Register Name: CCI_FMT_REG
Bit
R/W
Default/Hex
Description
31:25
R/W
0
SLV_ID
7bit address
24
R/W
0
CMD
0: write
1: read
23:20
R/W
1
ADDR_BYTE
How many bytes be sent as address
0~15
19:16
R/W
1
DATA_BYTE
How many bytes be sent/received as data
1~15
Normally use ADDR_DATA with 0_2, 1_1, 1_2, 2_1, 2_2 access mode. If
DATA bytes is 0, transmission will not start. In complete mode, the
ADDR_BYTE and DATA_BYTE is defined in a byte’s high/low 4bit.
15:0
R/W
1
PACKET_CNT
FIFO data be transmitted as PACKET_CNT packets in current format.
Total bytes not exceed 32bytes.
6.1.4.28. CCI Bus Control Register (Default Value: 0x00002500)
Offset: 0x300C
Register Name: CCI_BUS_REG
Bit
R/W
Default/Hex
Description
31:16
R/W
0
DLY_CYC
0~65535 FSCL cycles between each transmission
15
R/W
0
DLY_TRIG
0: disable
1: execute transmission after internal counter delay when triggered
14:12
R/W
0x2
CLK_N
CCI bus sampling clock F0=24MHz/2^CLK_N
11:8
R/W
0x5
CLK_M
CCI output SCL frequency is FSCL=F1/10=(F0/(CLK_M+1))/10
7
R
/
SCL_STA
SCL current status
6
R
/
SDA_STA
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