Owners manual

Interfaces

8.1. TWI

8.1.1. Overview

This TWI Controller is designed to be used as an interface between CPU host and the serial TWI bus. It can support all

the standard TWI transfer, including Slave and Master. The communication to the TWI bus is carried out on a byte-wise

basis using interrupt or polled handshaking. This TWI Controller can be operated in standard mode (100K bps) or

fast-mode, supporting data rate up to 400K bps. Multiple Masters and 10-bit addressing Mode are supported for this

specified application. General Call Addressing is also supported in Slave mode.

The TWI Controller includes the following features:

 Software-programmable for Slave or Master

 Support Repeated START signal

 Multi-master systems supported

 Allow 10-bit addressing with TWI bus

 Performs arbitration and clock synchronization

 Own address and General Call address detection

 Interrupt on address detection

 Support speeds up to 400Kbits/s (‘fast mode’)

 Allow operation from a wide range of input clock frequencies

8.1.2. Timing Diagram

Data transferred are always in a unit of 8-bit (byte), followed by an acknowledge bit. The number of bytes that can be

transmitted per transfer is unrestricted. Data is transferred in serial with the MSB first. Between each byte of data

transfer, a receiver device will hold the clock line SCL low to force the transmitter into a wait state while waiting the

response from microprocessor.

Data transfer with acknowledge is obligatory. The clock line is driven by the master all the time, including the

acknowledge-related clock cycle, except for the SCL holding between each bytes. After sending each byte, the

transmitter releases the SDA line to allow the receiver to pull down the SDA line and send an acknowledge signal (or

leave it high to send a "not acknowledge") to the transmitter.

When a slave receiver doesn't acknowledge the slave address (unable to receive because of no resource available), the

data line must be left high by the slave so that the master can then generate a STOP condition to abort the transfer.

Slave receiver can also indicate not to want to send more data during a transfer by leave the acknowledge signal high.

And the master should generate the STOP condition to abort the transfer.

Below diagram provides an illustration the relation of SDA signal line and SCL signal line on the TWI serial bus.

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