Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 442
IIC2IIC5IIC5IIC4IIC4IIC3IIC1
SDA
SCL
Figure 8-1. TWI Timing Diagram
8.1.3. TWI Controller Special Requirement
8.1.3.1. TWI Pin List
Port Name
Width
Direction
Description
TWI_SCL
1
IN/OUT
TWI Clock line
TWI_SDA
1
IN/OUT
TWI Serial Data line
8.1.3.2. TWI Controller Operation
There are four operation modes on the TWI bus which dictates the communications method. They are Master Transmit,
Master Receive, Slave Transmit and Slave Receive. In general, CPU host controls TWI by writing commands and data to
its registers. The TWI interrupts the CPU host for the attention each time a byte transfer is done or a START/STOP
conditions is detected. The CPU host can also poll the status register for current status if the interrupt mechanism is not
disabled by the CPU host.
When the CPU host wants to start a bus transfer, it initiates a bus START to enter the master mode by setting IM_STA bit
in the 2WIRE_CNTR register to high (before it must be low). The TWI will assert INT line and INT_FLAG to indicate a
completion for the START condition and each consequent byte transfer. At each interrupt, the micro-processor needs to
check the 2WIRE_STAT register for current status. A transfer has to be concluded with STOP condition by setting M_STP
bit high.
In Slave Mode, the TWI also constantly samples the bus and look for its own slave address during addressing cycles.
Once a match is found, it is addressed and interrupt the CPU host with the corresponding status. Upon request, the CPU
host should read the status, read/write 2WIRE_DATA data register, and set the 2WIRE_CNTR control register. After each
byte transfer, a slave device always halt the operation of remote master by holding the next low pulse on SCL line until
the microprocessor responds to the status of previous byte transfer or START condition.
8.1.4. TWI Controller Register List
Module Name
Base Address
R_TWI
0x01F02400
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