Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 443
TWI0
0x01C2AC00
TWI1
0x01C2B000
TWI2
0x01C2B400
Register Name
Offset
Description
TWI_ADDR
0x0000
TWI Slave address
TWI_XADDR
0x0004
TWI Extended slave address
TWI_DATA
0x0008
TWI Data byte
TWI_CNTR
0x000C
TWI Control register
TWI_STAT
0x0010
TWI Status register
TWI_CCR
0x0014
TWI Clock control register
TWI_SRST
0x0018
TWI Software reset
TWI_EFR
0x001C
TWI Enhance Feature register
TWI_LCR
0x0020
TWI Line Control register
8.1.5. TWI Controller Register Description
8.1.5.1. TWI Slave Address Register(Default Value: 0x00000000)
Offset: 0x00
Register Name: TWI_ADDR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:1
R/W
0
SLA
Slave address
 7-bit addressing
SLA6, SLA5, SLA4, SLA3, SLA2, SLA1, SLA0
 10-bit addressing
1, 1, 1, 1, 0, SLAX[9:8]
0
R/W
0
GCE
General call address enable
0: Disable
1: Enable
Notes:
For 7-bit addressing:
SLA6 – SLA0 is the 7-bit address of the TWI when in slave mode. When the TWI receives this address after a START
condition, it will generate an interrupt and enter slave mode. (SLA6 corresponds to the first bit received from the TWI
bus.) If GCE is set to ‘1’, the TWI will also recognize the general call address (00h).
For 10-bit addressing:
When the address received starts with 11110b, the TWI recognizes this as the first part of a 10-bit address and if the
next two bits match ADDR[2:1] (i.e. SLAX9 and SLAX8 of the device’s extended address), it sends an ACK. (The device
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