Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 444
does not generate an interrupt at this point.) If the next byte of the address matches the XADDR register (SLAX7 –
SLAX0), the TWI generates an interrupt and goes into slave mode.
8.1.5.2. TWI Extend Address Register(Default Value: 0x00000000)
Offset: 0x04
Register Name: TWI_XADDR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R/W
0
SLAX
Extend Slave Address
SLAX[7:0]
8.1.5.3. TWI Data Register(Default Value: 0x00000000)
Offset: 0x08
Register Name: TWI_DATA
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
R/W
0
TWI_DATA
Data byte for transmitting or received
8.1.5.4. TWI Control Register(Default Value: 0x00000000)
Offset: 0x0C
Register Name: TWI_ CNTR
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
0
INT_EN
Interrupt Enable
1’b0: The interrupt line always low
1’b1: The interrupt line will go high when INT_FLAG is set.
6
R/W
0
BUS_EN
TWI Bus Enable
1’b0: The TWI bus inputs ISDA/ISCL are ignored and the TWI Controller will
not respond to any address on the bus
1’b1: The TWI will respond to calls to its slave address – and to the general
call address if the GCE bit in the ADDR register is set.
Notes: In master operation mode, this bit should be set to ‘1’
5
R/W
0
M_STA
Master Mode Start
When M_STA is set to ‘1’, TWI Controller enters master mode and will
transmit a START condition on the bus when the bus is free. If the M_STA bit
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