Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 445
is set to ‘1’ when the TWI Controller is already in master mode and one or
more bytes have been transmitted, then a repeated START condition will be
sent. If the M_STA bit is set to ‘1’ when the TWI is being accessed in slave
mode, the TWI will complete the data transfer in slave mode then enter
master mode when the bus has been released.
The M_STA bit is cleared automatically after a START condition has been
sent: writing a ‘0’ to this bit has no effect.
4
R/W
0
M_STP
Master Mode Stop
If M_STP is set to ‘1’ in master mode, a STOP condition is transmitted on the
TWI bus. If the M_STP bit is set to ‘1’ in slave mode, the TWI will behave as
if a STOP condition has been received, but no STOP condition will be
transmitted on the TWI bus. If both M_STA and M_STP bits are set, the TWI
will first transmit the STOP condition (if in master mode) then transmit the
START condition.
The M_STP bit is cleared automatically: writing a ‘0’ to this bit has no effect.
3
R/W
0
INT_FLAG
Interrupt Flag
INT_FLAG is automatically set to ‘1’ when any of 28 (out of the possible 29)
states is entered (see ‘STAT Register’ below). The only state that does not set
INT_FLAG is state F8h. If the INT_EN bit is set, the interrupt line goes high
when IFLG is set to ‘1’. If the TWI is operating in slave mode, data transfer is
suspended when INT_FLAG is set and the low period of the TWI bus clock
line (SCL) is stretched until ‘1’ is written to INT_FLAG. The TWI clock line is
then released and the interrupt line goes low.
2
R/W
0
A_ACK
Assert Acknowledge
When A_ACK is set to ‘1’, an Acknowledge (low level on SDA) will be sent
during the acknowledge clock pulse on the TWI bus if:
1. Either the whole of a matching 7-bit slave address or the first or the
second byte of a matching 10-bit slave address has been received.
2. The general call address has been received and the GCE bit in the ADDR
register is set to ‘1’.
3. A data byte has been received in master or slave mode.
When A_ACK is ‘0’, a Not Acknowledge (high level on SDA) will be sent when
a data byte is received in master or slave mode.
If A_ACK is cleared to ‘0’ in slave transmitter mode, the byte in the DATA
register is assumed to be the ‘last byte’. After this byte has been
transmitted, the TWI will enter state C8h then return to the idle state (status
code F8h) when INT_FLAG is cleared.
The TWI will not respond as a slave unless A_ACK is set.
1:0
R/W
0
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