Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 447
8.1.5.6. TWI Clock Register(Default Value: 0x00000000)
Offset: 0x14
Register Name: TWI_CCR
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6:3
R/W
0
CLK_M
2:0
R/W
0
CLK_N
The TWI bus is sampled by the TWI at the frequency defined by F0:
Fsamp = F 0 = Fin / 2^CLK_N
The TWI OSCL output frequency, in master mode, is F1 / 10:
F1 = F0 / (CLK_M + 1)
Foscl = F1 / 10 = Fin / (2^CLK_N * (CLK_M + 1)*10)
For Example：
Fin = 48Mhz (APB clock input)
For 400kHz full speed 2Wire, CLK_N = 2, CLK_M=2
F0 = 48M/2^2=12Mhz, F1= F0/(10*(2+1)) = 0.4Mhz
For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11
F0=48M/2^2=12Mhz, F1=F0/(10*(11+1)) = 0.1Mhz
8.1.5.7. TWI Soft Reset Register(Default Value: 0x00000000)
Offset: 0x18
Register Name: TWI_SRST
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0
SOFT_RST
Soft Reset
Write ‘1’ to this bit to reset the TWI and clear to ‘0’ when completing Soft
Reset operation.
8.1.5.8. TWI Enhance Feature Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: TWI_EFR
Bit
R/W
Default/Hex
Description
31:2
/
/
/
0:1
R/W
0
DBN
Data Byte number follow Read Command Control
0— No Data Byte to be written after read command
1— Only 1 byte data to be written after read command
2— 2 bytes data can be written after read command
3— 3 bytes data can be written after read command
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