Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 448
8.1.5.9. TWI Line Control Register(Default Value: 0x0000_003A)
Offset: 0x20
Register Name: TWI_LCR
Bit
R/W
Default/Hex
Description
31:6
/
/
/
5
R
1
SCL_STATE
Current state of TWI_SCL
0 – low
1 - high
4
R
1
SDA_STATE
Current state of TWI_SDA
0 – low
1 - high
3
R/W
1
SCL_CTL
TWI_SCL line state control bit
When line control mode is enabled (bit[2] set), value of this bit decide the
output level of TWI_SCL
0 – output low level
1 – output high level
2
R/W
0
SCL_CTL_EN
TWI_SCL line state control enable
When this bit is set, the state of TWI_SCL is control by the value of bit[3].
0-disable TWI_SCL line control mode
1-enable TWI_SCL line control mode
1
R/W
1
SDA_CTL
TWI_SDA line state control bit
When line control mode is enabled (bit[0] set), value of this bit decide the
output level of TWI_SDA
0 – output low level
1 – output high level
0
R/W
0
SDA_CTL_EN
TWI_SDA line state control enable
When this bit is set, the state of TWI_SDA is control by the value of bit[1].
0-disable TWI_SDA line control mode
1-enable TWI_SDA line control mode
8.1.5.10. TWI DVFS Register(Default Value: 0x00000000)
Offset: 0x24
Register Name: TWI_DVFSCR
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2
R/W
0
MS_PRIORITY
CPU and DVFS BUSY set priority select
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