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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 449

0: CPU has higher priority

1: DVFS has higher priority

1

R/W

0

CPU_BUSY_SET

CPU Busy set

0

R/W

0

DVFC_BUSY_SET

DVFS Busy set

Notes:This register is only implemented in TWI0.

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