Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 450
8.2. SPI
8.2.1. Overview
The SPI is the Serial Peripheral Interface which allows rapid data communication with fewer software interrupts. It can
interface with up to four slave external devices or one single external master.The SPI module contains one 64x8
receiver buffer (RXFIFO) and one64x8 transmit buffer (TXFIFO). It can work at two modes: Master mode and Slave
mode.
The SPI includes the following features:
 Full-duplex synchronous serial interface
 Master/Slave configurable
 Programmable clock granularity
 Four chip selects to support multiple peripherals
 8-bit wide by 64-entry FIFO for both transmit and receive date
 Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable
 Interrupt or DMA supported
 Support single and dual read mode
8.2.2. SPI Timing Diagram
The serial peripheral interface master uses the SPI_SCLK signal to transfer data in and out of the shift register. Data is
clocked using any one of four programmable clock phase and polarity combinations.
During Phase 0, Polarity 0 and Phase 1, Polarity 1 operations, output data changes on the falling clock edge and input
data is shifted in on the rising edge.
During Phase 1, Polarity 0 and Phase 0, Polarity 1 operations, output data changes on the rising edges of the clock and
is shifted in on falling edges.
The POL defines the signal polarity when SPI_SCLK is in idle state. The SPI_SCLK is high level when POL is ‘1’ and it is low
level when POL is ‘0’. The PHA decides whether the leading edge of SPI_SCLK is used for setup or sample data. The
leading edge is used for setup data when PHA is ‘1’ and for sample data when PHA is ‘0’. The four kind of modes are
listed below:
SPI Mode
POL
PHA
Leading Edge
Trailing Edge
0
0
0
Rising, Sample
Falling, Setup
1
0
1
Rising, Setup
Falling, Sample
2
1
0
Falling, Sample
Rising, Setup
3
1
1
Failing, Setup
Rising, Sample
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