Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 452
SPI0
0x01C68000
SPI1
0x01C69000
Register Name
Offset
Description
SPI_GCR
0x04
SPI Global Control Register
SPI_TCR
0x08
SPI Transfer Control register
/
0x0c
reserved
SPI_IER
0x10
SPI Interrupt Control register
SPI_ISR
0x14
SPI Interrupt Status register
SPI_FCR
0x18
SPI FIFO Control register
SPI_FSR
0x1C
SPI FIFO Status register
SPI_WCR
0x20
SPI Wait Clock Counter register
SPI_CCR
0x24
SPI Clock Rate Control register
/
0x28
reserved
/
0x2c
reserved
SPI_MBC
0x30
SPI Burst Counter register
SPI_MTC
0x34
SPI Transmit Counter Register
SPI_BCC
0x38
SPI Burst Control register
SPI_TXD
0x200
SPI TX Data register
SPI_RXD
0x300
SPI RX Data register
8.2.5. SPI Register Description
8.2.5.1. SPI Global Control Register(Default Value: 0x00000080)
Offset: 0x04
Register Name: SPI_CTL
Bit
R/W
Default/Hex
Description
31
R/W
0
SRST
Soft reset
Write ‘1’ to this bit will clear the SPI controller, and auto clear to ‘0’ when
reset operation completes
Write ‘0’ has no effect.
30:8
/
/
/
7
R/W
1
TP_EN
Transmit Pause Enable
In master mode, it is used to control transmit state machine to stop smart
burst sending when RX FIFO is full.
1 – stop transmit data when RXFIFO full
0 – normal operation, ignore RXFIFO status
Note: Can’t be written when XCH=1
6:2
/
/
/
1
R/W
0
MODE
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