Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 453
SPI Function Mode Select
0: Slave Mode
1: Master Mode
Note: Can’t be written when XCH=1
0
R/W
0
EN
SPI Module Enable Control
0: Disable
1: Enable
8.2.5.2. SPI Transfer Control Register(Default Value: 0x00000087)
Offset: 0x08
Register Name: SPI_INTCTL
Bit
R/W
Default/Hex
Description
31
R/W
0x0
XCH
Exchange Burst
In master mode it is used to start SPI burst
0: Idle
1: Initiates exchange.
Write “1” to this bit will start the SPI burst, and will auto clear after finishing
the bursts transfer specified by BC. Write “1” to SRST will also clear this bit.
Write ‘0’ to this bit has no effect.
Note：Can’t be written when XCH=1.
30:14
/
/
/
13
R/W
0x0
SDM
Master Sample Data Mode
0 - Delay Sample Mode
1 - Normal Sample Mode
In Normal Sample Mode, SPI master samples the data at the correct edge
for each SPI mode;
In Delay Sample Mode, SPI master samples data at the edge that is half cycle
delayed by the correct edge defined in respective SPI mode.
12
R/W
0x0
FBS
First Transmit Bit Select
0: MSB first
1: LSB first
Note：Can’t be written when XCH=1.
11
R/W
0x0
SDC
Master Sample Data Control
Set this bit to ‘1’ to make the internal read sample point with a delay of half
cycle of SPI_CLK. It is used in high speed read operation to reduce the error
caused by the time delay of SPI_CLK propagating between master and slave.
0 – normal operation, do not delay internal read sample point
1 – delay internal read sample point
Note：Can’t be written when XCH=1.
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