Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 454
10
R/W
0x0
RPSM
Rapids mode select
Select Rapids mode for high speed write.
0: normal write mode
1: rapids write mode
Note：Can’t be written when XCH=1.
9
R/W
0x0
DDB
Dummy Burst Type
0: The bit value of dummy SPI burst is zero
1: The bit value of dummy SPI burst is one
Note：Can’t be written when XCH=1.
8
R/W
0x0
DHB
Discard Hash Burst
In master mode it controls whether discarding unused SPI bursts
0: Receiving all SPI bursts in BC period
1: Discard unused SPI bursts, only fetching the SPI bursts during dummy
burst period. The bursts number is specified by TC.
Note：Can’t be written when XCH=1.
7
R/W
0x1
SS_LEVEL
When control SS signal manually (SPI_CTRL_REG.SS_CTRL==1), set this bit to
‘1’ or ‘0’ to control the level of SS signal.
0: set SS to low
1: set SS to high
Note：Can’t be written when XCH=1.
6
R/W
0x0
SS_OWNER
SS Output Owner Select
Usually, controller sends SS signal automatically with data together. When
this bit is set to 1, software must manually write SPI_CTL_REG.SS_LEVEL to 1
or 0 to control the level of SS signal.
0: SPI controller
1: Software
Note：Can’t be written when XCH=1.
5:4
R/W
0x0
SS_SEL
SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
Note：Can’t be written when XCH=1.
3
R/W
0x0
SSCTL
In master mode, this bit selects the output wave form for the SPI_SSx signal.
Only valid when SS_OWNER = 0.
0: SPI_SSx remains asserted between SPI bursts
1: Negate SPI_SSx between SPI bursts
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