Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 455
Note：Can’t be written when XCH=1.
2
R/W
0x1
SPOL
SPI Chip Select Signal Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Note：Can’t be written when XCH=1.
1
R/W
0x1
CPOL
SPI Clock Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Note：Can’t be written when XCH=1.
0
R/W
0x1
CPHA
SPI Clock/Data Phase Control
0: Phase 0 (Leading edge for sample data)
1: Phase 1 (Leading edge for setup data)
Note：Can’t be written when XCH=1.
8.2.5.3. SPI Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x10
Register Name: SPI_IER
Bit
R/W
Default/Hex
Description
31:14
R
0x0
Reserved.
13
R/W
0x0
SS_INT_EN
SSI Interrupt Enable
Chip Select Signal (SSx) from valid state to invalid state
0: Disable
1: Enable
12
R/W
0x0
TC_INT_EN
Transfer Completed Interrupt Enable
0: Disable
1: Enable
11
R/W
0x0
TF_UDR_INT_EN
TXFIFO under run Interrupt Enable
0: Disable
1: Enable
10
R/W
0x0
TF_OVF_INT_EN
TX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
9
R/W
0x0
RF_UDR_INT_EN
RXFIFO under run Interrupt Enable
0: Disable
1: Enable
8
R/W
0x0
RF_OVF_INT_EN
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