Owners manual

Interfaces
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 456
RX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
7
R
0x0
Reserved.
6
R/W
0x0
TF_FUL_INT_EN
TX FIFO Full Interrupt Enable
0: Disable
1: Enable
5
R/W
0x0
TX_EMP_INT_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable
4
R/W
0x0
TX_ERQ_INT_EN
TX FIFO Empty Request Interrupt Enable
0: Disable
1: Enable
3
R
0x0
Reserved
2
R/W
0x0
RF_FUL_INT_EN
RX FIFO Full Interrupt Enable
0: Disable
1: Enable
1
R/W
0x0
RX_EMP_INT_EN
RX FIFO Empty Interrupt Enable
0: Disable
1: Enable
0
R/W
0x0
RF_RDY_INT_EN
RX FIFO Ready Request Interrupt Enable
0: Disable
1: Enable
8.2.5.4. SPI Interrupt Status Register(Default Value: 0x00000022)
Offset: 0x14
Register Name: SPI_INT_STA
Bit
R/W
Default/Hex
Description
31:14
/
0x0
/
13
R/W
0
SSI
SS Invalid Interrupt
When SSI is 1, it indicates that SS has changed from valid state to invalid
state. Writing 1 to this bit clears it.
12
R/W
0
TC
Transfer Completed
In master mode, it indicates that all bursts specified by BC has been
exchanged. In other condition, When set, this bit indicates that all the data
in TXFIFO has been loaded in the Shift register, and the Shift register has
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